1. Field of the Invention
The present invention relates to a high density electrically-erasable, programmable read-only-memory (EEPROM) cell array and, in particular, to a high-density EEPROM cell array which can selectively erase each byte of data in each row of the array.
2. Discussion of the Prior Art
The basic, fundamental challenge in creating an electrically-erasable programmable read only memory (EEPROM) cell is to use a controllable and reproducible electrical effect which has enough nonlinearity so that the memory cell can be written or erased at one voltage in less than 1 ms and can be read at another voltage, without any change in the programmed data for more than 10 years. Fowler-Nordheim tunneling, which was first described by Fowler and Nordheim in 1928, exhibits the required nonlinearity and has been widely used in EEPROM memories.
In silicon (Si), the energy difference between the conduction band and the valence band is 1.1 eV. In silicon dioxide (SiO.sub.2), the energy difference between these bands is about 8.1 eV, with the conduction band in SiO, 3.2 eV above that in Si. Since electron energy is about 0.025 eV at thermal room temperature, the probability that an electron in Si can gain enough thermal energy to surmount the Si-to-SiO.sub.2 barrier and enter the conduction band in SiO.sub.2 is very small. If electrons are placed on a polysilicon floating gate surrounded by SiO.sub.2, then this band diagram will by itself insure the retention of data.
Fowler-Nordheim emission, which was observed early in this century for the case of electron emission from metals into vacuums, was also observed by Lenzliger and Snow in 1969 for electron emission from silicon to silicon dioxide. In the presence of a high electric field at the Si-SiO.sub.2 interface, the energy bands will be distorted and there is a small, but finite, probability that an electron in the conduction band of the Si will quantum mechanically tunnel through the energy barrier and emerge in the conduction band of the SiO.sub.2.
The tunneling current increases exponentially with the applied field in accordance with the following general current density expression: EQU J=(AE2)exp(-B/E)
where
A and B ar constants, and PA1 E is the field at the Si-SiO.sub.2 interface
This current is observable at a current density of 10E-6 A/cm2 when the field at the Si-SiO.sub.2 interface is about 10 MV/cm. Local fields of this magnitude, at voltages practicable for use in microelectronics, can be obtained by applying a voltage across either a thin (about 100 .ANG.) oxide grown on bulk silicon or across thicker (about 500 .ANG.) oxide grown on polysilicon. In the latter case, the field enhancement arises from textured polysilicon formation, i.e. positive curvature regions at the polysilicon-polysilicon oxide interface resulting in tunneling enhancement at similar voltages as in the first case.
The theoretically ideal EEPROM memory cell comprises a single transistor addressable by applying electrical signals to a specified row and a specified column of the memory array matrix. For example, to write a logic "1" or a logic "0" into a cell of this "ideal" cell, a voltage is applied to the control gate corresponding to the row (word line) of the selected cell while a voltage corresponding to either a "1" or a "0" is applied to the source or drain corresponding to the column (bit line) of the selected cell.
An important problem encountered in attempts to realize this "ideal" cell is the need for an additional access transistor in each memory cell to enable selection of a single row of memory cells while changing data in the selected cell without accidentally writing or erasing memory in other rows. Unfortunately, the presence of an additional access transistor in each memory cell increases the size of the cell and leads to impractical die size for high density Megabit memory arrays.
It is, therefore, a goal to provide an EEPROM cell which does not require an additional distinct access transistor in each memory cell to provide reliable selection of a single cell for changing data while precluding accidental simultaneous programming or erasure in non-selected cells.
The basic concept of the well-known FLOTOX EEPROM memory cell is shown in FIG. 1. In the FLOTOX cell, the tunnel oxide, which typically is less than 100A thick, is grown over an area defined photolithographically in the drain region (or an extension of the drain region, called buried N+). Charging of the floating gate to program the cell is achieved by grounding the source and the drain and applying a high voltage to the control gate. The FLOTOX cell is designed such that a large fraction of the applied voltage is coupled across the tunnel oxide resulting in the transport of electrons from the drain to floating gate. Discharge of the floating gate to erase the cell is achieved by grounding the control gate, floating the source and applying a high voltage to the drain. In this case, most of the applied voltage is coupled across the tunnel oxide, but the field is reversed, resulting in tunneling of electrons from the floating gate to the drain. The source is floated so that there is no continuous current path, an important factor when an internal charge pump is used to generate the high voltage from a .ltoreq. 5 V supply.
If a single transistor memory cell is placed in a typical array with drains connected to metal columns and gates connected to common polysilicon word lines, the erasing of the cell, with the word line grounded, will mean that high voltage is applied to all drains in a common column. Erasing can be inhibited in non-selected cells by taking unselected word lines to a high voltage. However, this means that unselected cells along the same word line may be programmed. To avoid such disturb conditions, as shown in FIG. 1, the FLOTOX cell utilizes a distinct access transistor to isolate the drain from the column bit line. The access transistor is off for rows that are not selected.
FIG. 2 provides a layout of the FIG. 1 FLOTOX cell, with the FIG. 1 cross section being taken perpendicular to the word line (control gate) and through the tunnel oxide window.
E. K. Shelton, "Low-power EEPROM can be reprogrammed fast", Electronics, Jul. 31, 1980, pp. 89-92, discloses a basic EEPROM concept similar to the above-described FLOTOX concept. However, as shown in FIG. 3, instead of a tunnel oxide area defined lithographically over the drain (buried N+), the Shelton cell has its tunnelling area defined in the channel under the polysilicon floating gate. The polysilicon floating gate partially spans the drain side of the channel, while the remainder of the channel (source side) is spanned by an overlying aluminum control gate. The aluminum control gate is insulated from the polysilicon floating gate by a thin silicon nitride layer.
Furthermore, the Shelton memory cell is formed in a P-well on a N-substrate. Controlling the P-well potential allows the elimination of the distinct access transistor in each memory cell. The potential of the P-well and the sources and drains of the unselected cells are chosen during programming operations to prevent minority carriers from discharging any of the floating gates to the substrate while permitting an individual selected floating gate to be programmed.
Programming of the FIG. 3 cell is achieved by grounding the P-well and connecting the drain through a load resistance to the programming voltage. The source is connected to either the programming voltage or to ground depending upon whether a "1" or a "0" is to be stored. To initiate programming, the aluminum control gate is connected to the high voltage. If the source potential is also connected to the high voltage, then the internal access transistor doesn't turn on and the surface of the P-well below the floating gate is depleted of electrons. Only a small potential difference exists between the surface of the P-well and the floating gate. Therefore, no electrons tunnel into the gate and the cell remains in a 0 state. If the source terminal is connected to ground (to program a 1), then the internal access transistor turns on, the surface potential under the floating gate drops to close to 0 V, and electrons from the inversion layer tunnel through the thin oxide into the floating gate.
The FIG. 3 cell is erased by grounding the control gate and then raising the P-well to the programming voltage. This causes electrons to tunnel from the floating gate to the P-well via the tunnel oxide. As electrons tunnel through the tunnel oxide, the floating gate acquires a net positive charge.
Although the FIG. 3 Shelton cell differs from the FIG. 1 FLOTOX cell in that it does not utilize a distinct access transistor, it does require an internal access transistor and, thus, also requires a relatively large cell size.
As stated above, this application is a continuation-in-part of co-pending application Ser. No. 07/891,705 filed Jun. 1, 1992 for HIGH DENSITY EEPROM CELL ARRAY WITH NOVEL PROGRAMMING SCHEME AND METHOD OF MANUFACTURE. The co-pending application describes an EEPROM cell array which is formed in a P-well semiconductor region which, in turn, is formed in an N-type substrate.
As is well known, conventional EEPROMs, which are typically formed with 2.sup.n cells per row, e.g. 32, 64, 128 cells per row, can selectively erase each byte of data in each row of memory cells. In contrast, the EEPROM cell array described in the co-pending application cannot selectively erase each byte of data. When the bias voltages are applied to erase a memory cell, all of the memory cells in the same row are also erased.
As a result, the EEPROM array cannot be used in place of conventional EEPROMs when byte-wide erasure is required. Therefore, there is a need for a cell array as described in the co-pending application which can selectively erase each byte of data in each row of the array.